(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming mask read-only memory (ROM) devices in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Mask read-only memory (ROM) devices are memory arrays where the contents are permanently hard coded. Mask ROM is used, for example, for core or boot-up programming in microcomputer systems. Though the contents of the memory array cannot be altered, the mask ROM integrated circuit can be produced for less money than a comparably sized programmable device, such as electrically erasable programmable ROM (EEPROM). In addition, the data in a mask ROM is typically less prone to data errors resulting from programming problems or data loss due to environmental conditions.
The key technology in the mask ROM is typically the MOS transistor. Each cell in the mask ROM array is comprised of a MOS transistor. Each transistor has been pre-programmed to a given state during the manufacturing process. The state of the transistor, either logical "0" or "1," is determined by the fixed threshold voltage of the transistor.
Referring now to FIG. 1, a cross sectional representation of a prior art integrated circuit device is illustrated. The cross section shows a partially completed mask ROM device of the prior art. A semiconductor substrate 10 is shown. Field oxide (FOX) regions 14 have been defined in the semiconductor substrate 10. The active device area for the mask ROM is the area of the substrate 10 between the field oxide regions 14. A sacrificial oxide layer 18 has been formed overlying the semiconductor substrate 10.
In the typical prior art process, a coding implantation 26 is performed at this part of the mask ROM process. In the coding implantation 26, doping ions are implanted into the semiconductor substrate 10 where defined by the coding mask 22. The coding implantation 26 will alter the voltage threshold (V.sub.t) of the completed MOS transistor by creating a coding threshold region 30 near the surface of the semiconductor substrate 10 where the doping concentration is either greater or lesser than the comparable region in non-implanted devices.
A typical mask ROM scenario could be the assignment of a logical "1" to transistors with high V.sub.t and a logical "0" to transistors with low V.sub.t. If the ion implantation used in the coding implant will cause the V.sub.t to increase, then the mask used to pattern the photoresist 22 will have openings only overlying logical "1" transistors.
Referring now to FIG. 2, after the coding implantation, the sacrificial oxide layer 18 is removed. A gate oxide layer 32 is formed overlying the semiconductor substrate 10. A polysilicon layer 38 is deposited overlying the gate oxide layer 32. The polysilicon layer 38 and the gate oxide layer 32 are then patterned to form the gate electrode 38 for the mask ROM device. Additional processing steps for forming lightly doped drains, sidewall spacers , and source and drain junctions, would also occur but are not illustrated here.
Note that the coding implantation occurs relatively early in the mask ROM manufacturing sequence. This is an important observation. The data contents, often a microcomputer program, are permanently encoded into the mask ROM as soon as the coding implant is performed. If the designers of the mask ROM application require a programming change after the integrated circuit or circuit batch has passed the coding implantation, it is too late. The circuits either must be used as they were originally coded, or they must be scrapped. In practice, code changes are a common occurrence. Preferably, the coding process step would be as late in the processing sequence as possible. A relatively later coding step in the process helps to prevent scrap, provides better service to the applications customer, and increases the economic viability of the mask ROM manufacturer.
Several prior art approaches disclose methods to form mask ROM devices in the manufacture of an integrated circuit device. U.S. Pat. No. 5,378,647 to Hong discloses a method to form a mask ROM device using polysilicon bit lines and a back gate construction. The bit pattern is formed by selective removal of the polysilicon layer. U.S. Pat. No. 5,589,414 to Wann et al discloses a prior art method to code a mask ROM by selectively implanting the channel area through the polysilicon gate. Photoresist is used to protect non-implanted gates and source and drain regions. This invention also teaches a method to code a mask ROM where a thin first polysilicon gate layer is formed. The code implant is performed through the thin polysilicon gate. The second polysilicon layer is deposited, and the transistor is completed. U.S. Pat. No. 5,751,040 to Chen et al teaches a process to form a mask ROM device with a vertical channel. U.S. Pat. No. 5,831,314 to Wen discloses a process to form a trench-shaped ROM device.